发明名称 A/D converter calibration
摘要 A pipeline stage in a multi-bit/stage pipeline A/D converter is calibrated by switching a set of D/A converter unit-segments in the stage to predetermined states to produce a first digital signal. A second digital signal is produced by switching a predetermined unit-segment in the set to its complementary state and keeping the states of the other unit-segments in the set unchanged. The unit-segment is then associated with a calibration coefficient representing the deviation of the difference between the first and second digital signals from an expected difference between the first and second digital signals. This process is repeated for each unit-segment that is to be calibrated.
申请公布号 US6486807(B2) 申请公布日期 2002.11.26
申请号 US20010842390 申请日期 2001.04.25
申请人 TELEFONAKTIEBOLAGET LM ERICSSON 发明人 JONSSON BENGT ERIK
分类号 H03M1/44;H03M1/10;H03M1/16;(IPC1-7):H03M1/06 主分类号 H03M1/44
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