发明名称 COHERENT INSTRUCTION CACHE UTILIZING CACHE-OP EXECUTION RESOURCES
摘要 A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance operation. The first processor can determine whether the cache maintenance operation is a coherent operation. For coherent operations, the first processor sends a coherent request message for distribution to other processors in the coherent domain and can cancel execution of the cache maintenance operation pending receipt of intervention messages corresponding to the coherent request. The intervention messages can reflect a global ordering of coherence traffic in the multiprocessor system and can include instructions for maintaining a data cache and an instruction cache of the first processor. Cache maintenance operations that are determined to be non-coherent can be executed at the first processor without sending the coherent request.
申请公布号 US2009157981(A1) 申请公布日期 2009.06.18
申请号 US20080332291 申请日期 2008.12.10
申请人 MIPS TECHNOLOGIES, INC. 发明人 KINTER RYAN C.;JONES DARREN M.;KNOTH MATTHIAS
分类号 G06F12/08;G06F9/30 主分类号 G06F12/08
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