发明名称 MEMORY MANAGEMENT APPARATUS
摘要 <p>A second memory (130) holds data on a segment unit basis. An allocation control circuit (120) sets a buffer space as a logical address. The buffer space is formed as an aggregation of one or more segments. A state holding circuit (126) holds the correspondence relationship between the buffer space and the segments as segment allocation information. An address conversion circuit (128) converts a logical address to a physical address with reference to the segment allocation information. A segment queue holds an empty segment and a buffer queue holds an empty buffer. The state holding circuit (126) comprises a plurality of register groups each including a plurality of segment registers. The register group is made to correspond to any of a plurality of the buffer spaces. The segment register has a set range number for specifying a predetermined range of the logical address range in the relevant buffer space.</p>
申请公布号 WO2008084531(A1) 申请公布日期 2008.07.17
申请号 WO2007JP50131 申请日期 2007.01.10
申请人 NETCLEUS SYSTEMS CORPORATION;MARUYAMA, NAOTAKA 发明人 MARUYAMA, NAOTAKA
分类号 G06F12/02;G06F12/10 主分类号 G06F12/02
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