发明名称 Use of flash cache to improve tiered migration performance
摘要 For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target, and subsequent to the reading and the writing of the remaining data, destaging updates corresponding to the at least one data segment from either the higher and lower speed caches to the target.
申请公布号 US9471253(B2) 申请公布日期 2016.10.18
申请号 US201615015302 申请日期 2016.02.04
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Benhase Michael T;Gupta Lokesh M.
分类号 G06F12/10;G06F3/06;G06F12/08 主分类号 G06F12/10
代理机构 Griffiths & Seaton PLLC 代理人 Griffiths & Seaton PLLC
主权项 1. A system for data processing in a computing storage environment, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, comprising: a processor device, operable in the computing storage environment, wherein the processor device: at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, initiates a data migration mechanism by: copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level,reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target,subsequent to the reading and the writing of the remaining data, destaging updates corresponding to the at least one data segment from either the higher and lower speed caches to the target, andduring the reading and the writing of the remaining data, allowing destages of updates corresponding to the at least one data segment to proceed to the lower-speed cache in lieu of abstaining from destaging the updates to the source.
地址 Armonk NY US