Method and system for testing an integrated circuit featuring scan design.
摘要
<p>The present invention provides for improved testing of an integrated circuit 1. In order to measure a signal S in circuit 1 a multi-pattern is placed in shift register 70. The multi-pattern is generated by overlaying at least two test patterns Ax and Bx. Therefore the signal S changes its state in response to only a small amount of shift operations. <IMAGE></p>
申请公布号
EP0584385(A1)
申请公布日期
1994.03.02
申请号
EP19920114431
申请日期
1992.08.25
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
DIEBOLD, ULRICH;ROST, PETER;SCHMIDT, MANFRED;TORREITER, OTTO;VOGT, ROLF;WAGNER-DREBENSTEDT, KLAUS