Test circuit for synchronous integrated circuits, especially memory (DRAM) chips whereby test errors due to signal transfer time differences are minimized and the circuit is insensitive to signal voltage potential variations

摘要

Test circuit for a DUT comprises: (a) a test data generator (15) that generates reference test data as commanded by a control signal (b) a data output driver (25) for output of the generated reference test data and its delivery via a differential data bus to the DUT (c) a data input circuit for receipt of data from the DUT (d) a comparator circuit for comparison of the data from the DUT with the reference data to determine if it is operating correctly (e) whereby the data conducting pair (31, 36) of the differential data bus are configured to minimize signal transfer time differences. The differential data bus has one line carrying the data signal and the other the inverted signal with bus designed to minimize signal transfer time differences along the two lines.