Memory with bank-conflict-resolution (BCR) module including cache

摘要

A memory device includes a block of memory cells and a cache. The block of memory cells is a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.

主权项

1. A memory device comprising:
a block of memory cells that is a random access memory with multiple ports, the block of memory cells partitioned into a plurality of subunits that each has only a single port; a cache coupled to the block of memory cells, wherein:
the cache is adapted to store data;the cache is adapted to handle a plurality of accesses to the subunits of memory cells without a conflict such that the memory device appears to be a random access memory to the plurality of accesses;the cache contains validity data that indicates whether data stored in the cache is valid; anda read command is able to be performed without latency relative to a write command; and a bank-conflict resolution logic (BCR) that is adapted to:
test validity data of the data stored in the cache; andwrite a data word of the write command to a memory location of a memory bank in the memory partition if the validity data stored in the cache indicates that the data stored in the cache is invalid; and wherein:the block of memory cells is a memory partition; and
the subunit of memory cells is a memory banks.