发明名称 FRAME ALIGNER CIRCUIT
摘要 PURPOSE:To generate no slip phenomenon thereafter, when a prescribed time elapses after an alarm is released by comparing phases of a write pulse and a pulse of a read-out phase of wide width for a prescribed time, when the alarm from a device of a pre-stage is released. CONSTITUTION:A memory circuit 1 writes in data of a signal line 103 by a phase based on a write pulse of a signal line 107, and outputs data of a signal line 104 by a phase based on a read-out pulse of a signal line 108. An SEL 2 switches the data written in the circuit 1. A signal line 101 and 102 are signal lines of data WD1 and WD2 which have the same contents but whose frame phases only are different. An SEL 3 switches a write phase given to the circuit 1. Write pulses Wphi1, 2 denote frame phases of the data WD1, 2. At the time T1, a phase comparing circuit 4 detects an overlap of pulses of an input 107 and 110, and inverts a state of an output 111. Accordingly, after the time T1, the write pulse 107 and the read-out pulse 108 to the circuit 1 become a sufficiently separated phase relation, and a phase relation in which no slip phenomenon is generated is held.
申请公布号 JPH0427235(A) 申请公布日期 1992.01.30
申请号 JP19900131835 申请日期 1990.05.22
申请人 NEC CORP 发明人 KUDO TOSHIYUKI;NISHIKAWA KAZUO
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
代理机构 代理人
主权项
地址