发明名称 |
SEMICONDUCTOR MEMORY AND METHOD FOR CONTROLLING THE SAME |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor memory having a transfer system for transferring data synchronized with both edges of the leading and trailing of an outside clock signal, and yet easily being tested and evaluated by a conventional memory testing device with respect to SDRM for writing/reading data synchronously with the outside clock signal and a method for controlling the SDRAM and to provide a control method for the semiconductor memory. SOLUTION: This semiconductor memory is provided with a write amplifier controlling part 14 and an I/O data buffer/register 22 corresponding to the both data transfer systems of a DDR(double data rate) system and an SDR system as data transferring means. Also, a mode register 28 is used as a switching signal generating means for switching the data transferring means to either the DDR system or the SDR system.</p> |
申请公布号 |
JP2000182399(A) |
申请公布日期 |
2000.06.30 |
申请号 |
JP19980336708 |
申请日期 |
1998.11.27 |
申请人 |
FUJITSU LTD |
发明人 |
KANDA TATSUYA;TOMITA HIROYOSHI |
分类号 |
G11C11/413;G11C7/10;G11C8/04;G11C11/401;G11C11/407;G11C11/409;G11C29/00;G11C29/12;G11C29/14;(IPC1-7):G11C29/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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