发明名称 DELAY ESTIMATION METHOD AND DEVICE FOR CIRCUIT MODEL AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To estimate delay of a semiconductor integrated circuit including cell delay.SOLUTION: A circuit model for a simulation of a cell includes a current source model of the cell in which a resistance element is added. A first lamp voltage source is connected to an input side of the cell, and a second lamp voltage source is connected to an output side of the cell.SELECTED DRAWING: Figure 8
申请公布号 JP2016133903(A) 申请公布日期 2016.07.25
申请号 JP20150006984 申请日期 2015.01.16
申请人 FUJITSU LTD 发明人 LIU YU;KANAZAWA YUJI
分类号 G06F17/50 主分类号 G06F17/50
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