发明名称 |
Half select method and structure for gating rashba or spin hall MRAM |
摘要 |
The present disclosure generally relates to SHE-MRAM memory cells. A memory cell array comprises one or more memory cells, wherein each of the one or more memory cells comprises a gate electrode, an insulating layer, a spin orbit material electrode, a MTJ, and a top electrode parallel to the gate electrode. The gate electrode and the top electrode are perpendicular to the spin orbit material electrode. By applying a voltage to the gate electrode, passing a current along the spin orbit material electrode, and utilizing Rashba and/or spin hall effects, writability of select memory cells is enhanced, allowing for individual memory cells to be written upon without disturbing neighboring memory cells. Additionally, Rashba and/or spin hall effects in neighboring memory cells may be suppressed to ensure only the selected memory cell is written. |
申请公布号 |
US9490297(B1) |
申请公布日期 |
2016.11.08 |
申请号 |
US201514871118 |
申请日期 |
2015.09.30 |
申请人 |
HGST NETHERLANDS B.V. |
发明人 |
Braganca Patrick M.;Fidelis Garcia Andrei Gustavo |
分类号 |
G11C11/16;H01L27/22;H01L43/04;H01L43/06;H01L43/08;H01L43/10;H01L29/423;H01L21/28;G11C11/18 |
主分类号 |
G11C11/16 |
代理机构 |
Patterson & Sheridan, LLP |
代理人 |
Patterson & Sheridan, LLP |
主权项 |
1. A memory cell array, comprising:
a first gate electrode; a first top electrode disposed above and parallel to the first gate electrode; a first memory cell disposed between the first gate electrode and the first top electrode; a second memory cell disposed between the first gate electrode and the first top electrode, and wherein the second memory cell is disposed adjacent to and spaced from the first memory cell; a second gate electrode disposed adjacent and parallel to the first gate electrode; a first spin orbit material electrode disposed perpendicular to the first gate electrode and the second gate electrode, wherein the first spin orbit material electrode is disposed between the first gate electrode and the first memory cell; and a third memory cell disposed on the first spin orbit material electrode and the second gate electrode, wherein the third memory cell is disposed adjacent to and spaced from the first memory cell, wherein the first memory cell, the second memory cell, and the third memory cell each comprise a free layer, a barrier layer disposed on the free layer, and a fixed layer disposed on the barrier layer. |
地址 |
Amsterdam NL |