Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down

摘要

A static CMOS component is operated in a power-down state at the lowest possible voltage that maintains register and internal state levels of the component. A method of operating the static CMOS component includes the steps of selectively supplying a reference voltage at two voltage levels including an operating voltage level and a low reference voltage level, detecting an idle state of the static CMOS component and controlling the selectively supplying step to supply the low reference voltage in response to detection of the idle state. The low reference voltage level is substantially lower than the operating voltage level but is sufficient in voltage amplitude to maintain register and internal state levels of the static CMOS component. An electronic system which performs this method includes a programmable power supply source which selectively supplies an operating voltage and a low voltage which is substantially lower than the operating voltage. The system further includes a static CMOS component which is connected to the programmable power supply source by a power line carrying the selected alternative voltage. The system also includes a system controller connected to the programmable power supply by a power control line which selects the voltage applied to the static CMOS component and by a status line indicative of component status.