发明名称 Buried channel deeply depleted channel transistor
摘要 Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
申请公布号 US9478571(B1) 申请公布日期 2016.10.25
申请号 US201414286063 申请日期 2014.05.23
申请人 Mie Fujitsu Semiconductor Limited 发明人 Bakhishev Teymur;Wang Lingquan;Zhao Dalong;Ranade Pushkar;Thompson Scott E.
分类号 H01L21/336;H01L27/146;H01L29/78;H01L29/66 主分类号 H01L21/336
代理机构 Baker Botts L.L.P. 代理人 Baker Botts L.L.P.
主权项 1. A method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate having one or more first device regions of a first conductivity type; adding at least one first dopant of the first conductivity type into at least one of the first device regions to define a screening layer of the first conductivity type at the surface of the semiconductor substrate and having an effective doping density that is substantially higher than an effective doping density of the first device regions; forming a substantially undoped layer of semiconducting material at least over the at least one of the first device regions; adding at least one second dopant of a second conductivity type into the substantially undoped layer over the at least one of the first device regions to define a channel layer above the screening layer; and forming gate structures and associated source and drain regions of the second conductivity type separated by a channel length in the first device regions to define MOSFET devices.
地址 Kuwana, Mie JP
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