| 摘要 |
PURPOSE: A timer circuit is provided to improve performance and compatibility thereof. CONSTITUTION: Disclosed is a timer circuit comprising a controller(2), a mode detector(3), a period/limit value applier(4), a first counting/comparing part(6), a second counting/comparing part(8) and an interrupt generator(7). The controller(2) stores data of input address to a register, and outputs a mode signal, a first and second period values of output time according to the stored data. The mode detector(3) outputs a mode signal of timer operation according to the mode signal from the controller(2). The period/limit value applier(4) periodically outputs the first and second period values according to the mode signal from the mode detector(3). The first counting/comparing part(6) counts a clock signal, and compares the first period values from the period/limit value applier(4) with the counting result data. The second counting/comparing part(8) counts the clock signal, and compares the second period values from the period/limit value applier(4) with the counting result data. The interrupt generator(7) outputs a first and a second interrupt signals according to a first and a second enable signals from the controller(2). The first and a second enable signals from the controller(2) are controlled by output signals of the first and second counting/comparing part(6, 8).
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