| 摘要 |
PROBLEM TO BE SOLVED: To reduce the non-etched area on the side face of a lower electrode of a capacitance element by patterning a second conductive film to form upper electrodes of the elements and patterning a first conductive film to the lower electrodes of the elements. SOLUTION: An insulating film 8 is formed on a first layer polycrystalline Si film 6, then a second layer polycrystalline Si film is formed and etched to form upper electrodes 9 of capacitance elements, using a resist mask 10, a photoresist H3 is formed to cover NMOS forming regions, resistance element forming regions, and capacitance element forming regions on a Si substrate 1, p-type regions 12 are formed on the first layer polycrystalline Si film 6 on PMOS forming regions on the substrate 1, and the first layer polycrystalline Si film 6 is etched to form NMOS and PMOS gate electrodes, lower electrodes of the capacitance elements and resistance elements.
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