Power converter package including top-drain configured power FET

摘要

In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.

主权项

1. A semiconductor package comprising:
a top-drain vertical FET in a first active die, a source of said top-drain vertical FET situated on a source side of said first active die and a drain and a gate of said top-drain vertical FET situated on a drain side of said first active die; a bottom-drain vertical FET in a second active die, a source and a gate of said bottom-drain vertical FET situated on a source side of said second active die and a drain of said bottom-drain vertical FET situated on a drain side of said second active die; a conductive carrier attached to said source side of said first active die and to said drain side of said second active die; said conductive carrier coupling said source of said top-drain vertical FET to said drain of said bottom-drain vertical FET; and a patterned dielectric formed over said drain side of said first active die and said source side of said second active die, said patterned dielectric exposing said drain and said gate of said top-drain vertical FET and said source and said gate of said bottom-drain vertical FET.