Transistor structure with silicided source and drain extensions and process for fabrication

摘要

A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch.

主权项

1. An integrated circuit comprising:
a transistor formed in a semiconductor substrate, said transistor including:
a gate formed over a channel region in said substrate;source/drain extension regions formed in said substrate adjacent said channel region;source/drain regions formed in said substrate, said source/drain regions adjacent said source/drain extension regions and spaced from said channel region by said source/drain extension regions, said source/drain regions extending deeper into said substrate than said source/drain extension regions;a region of silicide formed on said source/drain extension regions and said source/drain regions, said region of silicide having a first thickness over said source/drain extension regions and a second thickness over said source/drain regions, said second thickness being greater than said first thickness; anda sidewall spacer extending over a portion of the region of silicide on the source/drain extension regions; and a conformal etch stop layer over the gate, source/drain extension regions and source/drain regions; a pre-metal dielectric layer over the conformal etch stop layer; and a contact extending through the pre-metal dielectric layer and the conformal etch stop layer to both the region of silicide having the first thickness and the region of silicide having the second thickness.