发明名称 GRAPHIC PROCESSOR
摘要 PROBLEM TO BE SOLVED: To place respective circuits in correct operation by guaranteeing memory access time in the worst case for circuits which need to finish processes within a prescribed time without fail when an integrated memory system is employed. SOLUTION: A bus control circuit 200 performs bus arbitration while sequentially switching a priority decision circuit A210 and a priority decision circuit B220 which differ in priority in bus arbitration timing. Consequently, even when circuits which need to gain memory access within the prescribed time without fail like a display circuit 340 and a video input circuit 330 are incorporated, the memory access time can be guaranteed even in the worst case for the respective circuit, so the circuits can be placed in correct operation.
申请公布号 JP2000181432(A) 申请公布日期 2000.06.30
申请号 JP19980352269 申请日期 1998.12.11
申请人 HITACHI LTD 发明人 SHIMOMURA TETSUYA;JO MANABU;MATSUO SHIGERU;NAKATSUKA YASUHIRO;YAMAGISHI KAZUSHIGE
分类号 G09G5/00;(IPC1-7):G09G5/00 主分类号 G09G5/00
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