Clock state control for power saving in an integrated circuit

摘要

Sequential logic elements may consume less static power in response to a first state of a clock signal than in response to a second state of a clock signal (the first and second state may be either low or high depending on the type of sequential logic). This can be exploited to reduce static power consumption of an integrated circuit by controlling the level of a clock signal so that is in the first state for a greater amount of time than the second state.

主权项

1. An integrated circuit comprising:
at least one sequential logic element; and clock supply circuitry configured to supply a clock signal to the at least one sequential logic element, wherein the clock supply circuitry comprises at least one clock gate configured to:
receive an enable signal; andreceive an input clock signal, wherein the input clock signal is in a first state of the input clock signal for a greater fraction of each clock cycle than a second state of the input clock signal; wherein in response to a first state of the clock signal, the at least one sequential logic element is configured to consume less static power than in response to a second state of the clock signal; and wherein the clock supply circuitry is configured to supply the first state of the clock signal to the at least one sequential logic element for a greater amount of time than the second state of the clock signal.