| 摘要 |
PROBLEM TO BE SOLVED: To provide a unit and method for load control which cause no trouble to a device by making it possible to start load control operation after the output of an FPGA(field programmable gate array), etc., is determined normally as to a unit and a method for load control which uses a device, such as an FPGA, where a program can be written. SOLUTION: A counter is provided which starts counting at starting of a CPU after being powered ON, and measures the time needed for the FPGA to end program loading. When the counter reaches a specific value, a reset signal is outputted to the FPGA, whose port output is determined. Once the output is determined, the FPGA outputs a standby signal to the CPU, which is able to confirm the normal start of the FPGA from the reception of the standby signal. |
