Method for manufacturing semiconductor device and device manufactured by the same

摘要

A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.

主权项

1. A method for manufacturing a semiconductor device, comprising:
providing a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates, the adjacent first gates and the adjacent second gates separated by an insulation, wherein a top surface of the insulation has a plurality of recesses, and the insulation comprises a plurality of spacers formed at sidewalls of each of the first and second gates, and a contact etch stop layer (CESL) formed at outsides of the spacers; forming a capping layer over the first gates, the second gates and the insulation, and filling the recesses; and removing the capping layer until reaching the top surface of the insulation, so as to form a plurality of insulating depositions to fill up the recesses, wherein upper surfaces of the insulating depositions are positioned above and spaced apart from a top surface of the CESL and top surfaces of the spacers, the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation, and the upper surfaces of the insulating depositions are parallel to top surfaces of the plurality of first gate and the plurality of second gates.