Non-volatile memory cell devices and methods, having a storage cell with two sidewall bit cells

摘要

Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data.

主权项

1. An apparatus, comprising:
an array of non-volatile storage cells formed in a portion of a semiconductor substrate, comprising:
a first storage cell having a first bit cell for storing trapped charges corresponding to a first data bit and a second bit cell for storing trapped charge corresponding to a second data bit, the first data bit and the second data bit being representative of different data bits;a second storage cell having a third bit cell for storing trapped charges corresponding to a third data bit and a fourth bit cell for storing trapped charge corresponding to a fourth data bit, the third data bit and the fourth data bit being representative of different data bits, the third data bit being a complementary data bit to the first data bit, the first and second storage cells comprising a first MOS transistor and a second MOS transistor, respectively, the first and second bit cells comprising first sidewall storage cells adjoining sidewalls of a first gate of the first MOS transistor, the third and fourth bit cells comprising second sidewall storage cells adjoining sidewalls of a second gate of the second MOS transistor, the first sidewall storage cells comprising first oxide-nitride-oxide layers adjoining sidewalls of the first gate, at least an oxide portion of the first oxide-nitride-oxide layers being a single continuous layer extending across a top surface from one sidewall to an opposite sidewall of the first gate of the first MOS transistor, the second sidewall storage cells comprising second oxide-nitride-oxide layers adjoining sidewalls of the second gate, at least an oxide portion of the second oxide-nitride-oxide layers being a single continuous layer extending across a top surface from one sidewall to an opposite sidewall of the second gate of the second MOS transistor;a word line coupled to supply voltages to gate terminals of the first and second storage cells; anda column multiplexer coupled to a plurality of column lines, a first column line coupled to a first source/drain terminal of the first storage cell and a second column line coupled to a first source/drain terminal of the second storage cell, the column multiplexer coupled to receive data and complementary data for storage in the non-volatile storage cells, the column multiplexer coupling a voltage to the first column line corresponding to the data, and coupling a voltage to the second column line corresponding to the complementary data.