| 摘要 |
The clock generating portion of a communication system includes a low-power, high-jitter phase locked loop (PLL) and a high-power, low-jitter PLL. Control logic within the chip allows for selective switching between the low-power and high-power PLL for receiving the broadcast signals, such as mobile TV signals. The switching may occur in a manner that is dependent on the conditions of the wireless channel and/or the complexity of the modulation scheme being used. The switching may be used to provide an oscillating signal from one or both of the PLLs to a receiver to be used to receive communication signals. The control logic may power off one of the PLLs to save power when not in use. |
