发明名称 |
Running state power saving via reduced instructions per clock operation |
摘要 |
A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial vs. parallel cache access and single vs. multiple instruction issue, retire, translation and/or formatting per clock cycle. The actions may be instituted only if additional conditions exist, such as residing in the lowest performance running state for a minimum time, not running in a higher performance state for more than a maximum time, a user did not disable the feature, the microprocessor supports multiple running states and the operating system supports multiple running states. |
申请公布号 |
US9442732(B2) |
申请公布日期 |
2016.09.13 |
申请号 |
US201313777104 |
申请日期 |
2013.02.26 |
申请人 |
VIA TECHNOLOGIES, INC. |
发明人 |
Henry G. Glenn;Parks Terry |
分类号 |
G06F9/30;G06F1/32 |
主分类号 |
G06F9/30 |
代理机构 |
|
代理人 |
Davis E. Alan;Huffman James W.;Cernyar Eric W. |
主权项 |
1. A microprocessor configured to transition through a plurality of performance running states, ranging between lowest and highest, each comparatively characterized by differences in clock frequencies and/or voltage levels, the microprocessor comprising:
functional units; and control registers, writeable to cause the functional units to institute one or more power-saving actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state; wherein the lowest performance running state comprises a non-sleeping state in which the microprocessor runs at its lowest supported clock frequency; wherein the microprocessor is configured with microcode to write the control registers to institute the one or more instructions-per-clock rate reducing actions, wherein the microcode is invoked in response to an instruction instructing the microprocessor to transition to the lowest performing running state. |
地址 |
New Taipei TW |