High voltage lateral SOI-DMOS transistor for an IC has a drift space covered with a thin passivating silicon dioxide layer and overlying thicker silicon nitride and CVD oxide layers

摘要

A high voltage lateral DMOS transistor has a drift space covered with a thin passivating SiO2 layer and overlying thicker Si3N4 and CVD oxide layers. A high voltage lateral DMOS transistor formed using a thin single crystal semiconductor layer on an insulating substrate comprises a heavily doped source/drain region, an adjoining lightly doped first semiconductor region in the form of a transistor control space covered with a thin gate insulation, a relatively lightly doped second semiconductor region of the same conductivity type as the source/drain region in the form of a transistor drift space covered with a thick dielectric, an adjoining heavily doped drain region of the same conductivity type and a preferably polysilicon or polycide control gate over the first semiconductor region and parts of the second semiconductor region. The thick dielectric comprises a sequence of a thin drift region-passivating SiO2 layer, a thicker Si3N4 layer and a thicker CVD oxide layer. An Independent claim is also included for production of the above lateral DMOS transistor.