| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase comparison circuit which has a short delay time and can reliably prevent a malfunction of a post-stage circuit even when a metastable occurs. <P>SOLUTION: A D-F/F 21 reads an external clock signal CLK1 on the basis of a control clock signal RCLK. Inverters INVA1, INVB1 having difference threshold level inverts the output of an inverter 22 to output it. Inverters INVA2, INVB2 having hysteresis characteristics inverts the outputs of inverters INVA1, INVB1 to output it. When the outputs of the inverters INVA2, INVB2 are coincident, an EX-NOR circuit 30, a D-latch 31 and an AND gate 32 add the output of the delay circuit 33 to a D-FF23 and a delay circuit 34, and if not coincident, turn off the outputs. The D-F/F23 reads the output of the inverter 22 on the basis of a delay signal of the control clock signal RCLK to be supplied via the AND gate 32, and outputs the read output. <P>COPYRIGHT: (C)2008,JPO&INPIT |
