发明名称 |
Circuit and method for improving ESD tolerance and switching speed |
摘要 |
Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance. |
申请公布号 |
US9406695(B2) |
申请公布日期 |
2016.08.02 |
申请号 |
US201414521378 |
申请日期 |
2014.10.22 |
申请人 |
Peregrine Semiconductor Corporation |
发明人 |
Shapiro Eric S.;Allison Matt |
分类号 |
H01L29/66;H01L21/82;H01L27/12;H01L27/02;H01L29/10 |
主分类号 |
H01L29/66 |
代理机构 |
Jaquez Land Greenhaus LLP |
代理人 |
Jaquez Land Greenhaus LLP ;Jaquez, Esq. Martin J.;Land, Esq. John |
主权项 |
1. An electronic circuit including:
a. a field effect transistor (FET) having a gate, a drain, a source, and a body; b. a gate resistor series connected to the gate of the FET; c. an accumulated charge sink (ACS) circuit connected to the body of the FET; and d. an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of the FET at a node opposite to the connection of the gate resistor to the gate. |
地址 |
San Diego CA US |