Flash memory unit and memory array, and programming, erasing and reading method thereof

摘要

A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

主权项

1. A memory array comprising:
a plurality of memory units arranged in M rows and N columns, 2N bit lines, M word lines, and 2M control lines, wherein:
M≧1;N≧1;N is an integer multiple of 8; wherein, for each memory unit of the plurality of memory units:
the memory unit is a flash memory unit including a semiconductor substrate, a first bit line structure, a second bit line structure, a word line structure, a first float gate, a second float gate, a first control gate, and a second control gate;the semiconductor substrate includes a first doping well and a second doping well formed in the semiconductor substrate, the first doping well and the second doping well respectively constituting a source and a drain;the first bit line structure and the second bit line structure are disposed on the semiconductor substrate and respectively connected with the source and the drain;the word line structure is disposed on the semiconductor substrate and between the first bit line structure and the second bit line structure;the first float gate is disposed on the semiconductor substrate and between the first bit line structure and the word line;the second float gate is disposed on the semiconductor substrate and between the second bit line structure and the word line;the first control gate is disposed on the first float gate;the second control gate is disposed on the second float gate; wherein, for each of the memory units in an nth column, the first bit line structure and the second bit line structure are respectively connected to two of the 2N bit lines wherein 1≦n≦N; and wherein, each of the memory units in the same row, the word line structure is connected to one of the M word lines in the memory array, and the first control gate and the second control gate are respectively connected to two of the 2M control lines.