| 摘要 |
PROBLEM TO BE SOLVED: To prevent the trouble of device operation due to a difference in the time needed for an actuating process by resetting a control means in response to power-ON operation and resetting a program-writable data device a specific time later. SOLUTION: When the power source is turned on, a reset signal RESET* is outputted from a reset circuit 101 to a CPU 102. When the reset signal is released a reset time later, the CPU 102 accesses a program ROM 104 to load a program for actuation. After the CPU 102 completes the loading of the program, an internal counter 103 of the CPU 102 begins to count. The CPU 102 outputs a reset signal FPGA-RST* to FPGA 105 a specific time later, i.e., when the counter 103 reaches a count value corresponding to the time or longer than that needed for FPGA 105 to complete the loading of the program from a program ROM 106 from a program ROM 106 for FPGA.
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