发明名称 |
Method of fabricating a memory cell for a static random access memory |
摘要 |
A method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.
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申请公布号 |
US6486007(B2) |
申请公布日期 |
2002.11.26 |
申请号 |
US20010910396 |
申请日期 |
2001.07.20 |
申请人 |
STMICROELECTRONICS, INC. |
发明人 |
CHAN TSIU CHIU;ZAMANIAN MEHDI;MCCLURE DAVID CHARLES |
分类号 |
G11C11/412;H01L21/8244;(IPC1-7):H01L21/335 |
主分类号 |
G11C11/412 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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