NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS CONTROL METHOD

摘要

PROBLEM TO BE SOLVED: To increase write operation speed by enabling simultaneous verification of many bits when a program is verified.

SOLUTION: The source line SL of a memory cell Trm formed in the N well of a memory cell array 11 is connected commonly to a column source line CSL being a source line in a block and a block source source line BSL in common, and is connected to a source line MSL outside the block via a block source select gate BSSG. This source line MSL outside the block is a metal layer of the upper most layer and wired so as to be extended in a Y axis direction (bit line direction). A cell current made to flow from the bit line by the output of a column latch via a memory cell of write complete when verifying the program is bypassed by the source line MSL outside the block.

COPYRIGHT: (C)2007,JPO&INPIT