发明名称 |
Parallel access virtual channel memory system with cacheable channels |
摘要 |
A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.
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申请公布号 |
US6167486(A) |
申请公布日期 |
2000.12.26 |
申请号 |
US19960746829 |
申请日期 |
1996.11.18 |
申请人 |
NEC ELECTRONICS, INC. |
发明人 |
LEE, JEFFERY H.;ANDO, MANABU |
分类号 |
G06F12/00;G06F12/06;G06F12/08;G11C11/401;(IPC1-7):G06F13/16 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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