发明名称 |
Semiconductor memory device using one common address bus line between address buffers and column predecoder |
摘要 |
A semiconductor memory device, includes: an external address buffer for buffering a first address signal to generate a buffered address signal; a delay for delaying the buffered address signal for a predetermined time to generate a delayed address signal; an internal address buffer for buffering the buffered address signal and the delayed address signal to generate a second address signal; a common address bus line; a switching unit responsive to a control signal for selectively coupling one of the buffered address signal, the delayed address signal and the second address signal as a selected address signal to said common address bus line; and a column predecoder for predecoding the selected address signal transferred via said common address bus line.
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申请公布号 |
US6166988(A) |
申请公布日期 |
2000.12.26 |
申请号 |
US19990471109 |
申请日期 |
1999.12.23 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
RYU, JE-HUN;HAN, JONG-HEE |
分类号 |
G11C11/408;G11C8/06;G11C11/407;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/408 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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