Integrated circuits having low power, low interference and programmable delay generators therein and methods of operating same

摘要

A programmable delay generator includes a calibration circuit and a delay line responsive to a calibration control signal generated by the calibration circuit. The calibration circuit includes a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein. A frequency of the DCO is set by the calibration control signal. The delay line includes a second plurality of delay stages that are replicas of the first plurality of delay stages. The calibration circuit may include a current steering digital-to-analog converter (CSDAC), which is responsive to a digital calibration code, and a current-to-voltage converter, which is responsive to at least one current signal generated by the CSDAC. The DCO and other portions of the calibration circuit are disabled into a low power state upon completion of a calibration operation, which may commence upon start-up.

主权项

1. A programmable delay generator, comprising:
a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit during a calibration operation; and a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit upon conclusion of the calibration operation when said DCO is powered-down into an inactive state.