Low voltage turn-on SCR for ESD protection

摘要

An apparatus and method are disclosed for enhancing the operation of an ESD protective circuit in a VLSI chip with a combination of elements for an SCR that lower the turn-on voltage of the SCR below the oxide breakdown voltage of the CMOS devices in the VLSI circuits. A low voltage trigger source is provided for the SCR by forming an N+-P-LDD junction between the SCR and a CMOS device incorporated therein. The prior art N-channel device used in triggering the known LVTSCR is modified by removing the rate electrode and thin oxide and implanting, adjacent the N+ drain region, a P-type lightly doped drain (P-LDD) region in the substrate to form the N+-P-L.DD junction. The turn-on voltage of this N+-P-LDD junction can be made lower than the oxide breakdown voltage of the CMOS devices by adjusting the P-LDD dosage. Junction breakdown causes a forward bias resulting in turn ON of the PNP bipolar device followed by turn ON of the interconnected NPN bipolar device to produce the high current flow through the SCR. Concern about damage to the gate oxide of the prior art NMOS is obviated as there is no longer a gate oxide.