| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To obtain a larger capacitor capacity for a prescribed area. <P>SOLUTION: In this method for forming a semiconductor integrated circuit structure, sloped sidewalls are formed on a DRAM storage cell by utilizing a dry plasma etching method like electron cyclotron resonance (ECR). It is possible to deposit an advanced dielectric material without generating substantial cracks by rounded corners of a lower electrode formed by the method. Further, it is possible to predict strictly and control capacitance by uniformity when forming the advanced dielectric material. In one embodiment, there is provided a method for forming a micro electronic circuit structure including a support layer (for example, an Si substrate 30) having a main face, a lower electrode overlapping the main face of the support layer, and a layer with a high-dielectric constant material (for example, a BST 44) overlapping the upper face of the lower electrode. The lower electrode has a barrier layer (for example, TiN 36) and a nonreactive layer (for example, Pt 42). <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
