| 摘要 |
A test pattern of a semiconductor device and a method for forming the same are provided to keep a current from escaping through a well, and prevent an SAC(Self-Aligned Contact) fail of a landing plug. A method for forming a test pattern of a semiconductor device comprises the steps of: forming an isolation layer which defines an active region on a semiconductor substrate(111) except for an expected region of test pattern; forming a photosensitive layer pattern coating an upper surface of the expected region of test pattern; ion-implanting dopants into an active region using the photosensitive layer pattern as a mask; removing the photosensitive layer pattern for defining a test pattern region; forming line-type landing plugs(113a,113b) in a direction towards a gate in a cell region on the semiconductor substrate; forming a first interlayer dielectric including a bit line contact plug(115) on the landing plug; forming a second interlayer dielectric including a bit line on the first interlayer dielectric; and forming a third interlayer dielectric including a storage node contact plug(119) on the second interlayer dielectric.
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