| 摘要 |
The data flows of a system are allocated an arithmetic or logical function per function block (ALU-block), forming a RAM control. The ALU-blocks are specialized according to individual processing tasks of the data flows. The current status of the Ram address and RAM output data are recoupled with the ALU-blocks. During operation, the ALU-blocks alternately produce write accesses to the RAM and read accesses of all the ALU blocks can occur with every cycle, thereby controlling the outgoing signal lines of the data flows. Registers are inserted in such a way that the ALU-blocks are placed between register levels to ensure that test patterns are generated automatically with existing CAE programs. The low use of test structures guarantees that the base circuit has good testability with a minimal test pattern rate at an early stage of the circuit design. The inventive circuit structure can also be configured as a digital signal processor. |
