FORWARDED CLOCK JITTER REDUCTION

摘要

In some embodiments, a differential amplifier with duty cycle correction is provided.

主权项

1. An apparatus comprising:
a first input node; a first termination resistor coupled to the first input node and a reference node; a second input node; a second termination resistor coupled to the second input node and the reference node; a first amplifier to receive first and second signals from the first and second input nodes, respectively; a second amplifier coupled to the first amplifier, the second amplifier to receive a differential output of the first amplifier and to provide an amplified output; and a digital offset cancellation circuit coupled to the second amplifier and the first amplifier.