Low insertion delay clock doubler and integrated circuit clock distribution system using same

摘要

A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.

主权项

1. A clock doubler comprising:
a first NAND gate having a first input for receiving a clock input signal, a second input, and an output; a second NAND gate having a first input, a second input for receiving a complement of said clock input signal, and an output, wherein the clock doubler provides a clock output signal in response to the outputs of said first and second NAND gates; an inverter chain having an input for receiving said clock input signal and responsive to first and second control signals to selectively provide a first true output to said first input of said second NAND gate, and a second complementary output to said second input of said first NAND gate; and a control signal generation circuit for providing said first and second control signals in response to said outputs of said first and second NAND gates.