Floating point multiply-add-substract implementation

摘要

A floating point multiply and addition/subtraction implementation is provided. Two operands are received in a standard floating point format with a code selecting a mathematic operation from addition, subtraction, and multiplication. Result mantissas and exponents are calculated simultaneously for all operations. The implementation simplifies computation of a result mantissa by dropping the least significant bits of the operands before computing the result. Underflow and overflow errors are shown by two extra bits in the exponent portion of the result. The mantissa result and the exponent result are selected by providing the operation code to a mantissa multiplexer and an exponent multiplexer. The selected mantissa and exponent are combined as output.

主权项

1. An apparatus for computing a multiplication, an addition or a subtraction of two operands A and B in floating point format having mantissas and exponents to give one of a multiplication, an addition or a subtraction result selected by a user supplied opcode comprising:
a mantissa multiplier joined to receive the mantissas of A and B and to provide a product of the mantissas; an multiplication exponent adder joined to receive the exponents of A and B and to calculate a multiplication preliminary result exponent as a sum of the exponents, said multiplication exponent adder storing at least one additional exponent bit more than the maximum number of exponent bits for the floating point format; an XOR gate joined to receive the signs of A and B and to calculate an output sign as the exclusive OR of the signs of A and B to provide a multiplication output sign; a priority encoder joined to receive the product of the mantissas and to provide the order of the product; shift logic joined to receive the order of the product and to provide a number of shifts required for an output mantissa in the floating point format; a mantissa shift register joined to receive the product of the mantissas and the number of shifts, the mantissa shift register shifting the product of the mantissas by dropping the least significant digits of the product in order to fit the product of the mantissas into the places available for the output mantissa in the floating point format and to provide the shifted product of the mantissas as the mantissa of the multiplication result; a combiner is joined to receive the mantissa of the multiplication result and the multiplication output sign and to provide a signed multiplication result; an addition/subtraction comparator joined to receive the exponents of A and B and to calculate the greater exponent to provide an addition/subtraction preliminary result exponent, said addition/subtraction comparator storing at least one additional exponent bit more than the maximum number of exponent bits for the floating point format as the addition/subtraction preliminary result exponent; an addition/subtraction exponent subtractor joined to receive the exponents of A and B and capable of providing a scale difference between A and B; a register receiving the mantissas of A and B and the scale difference, said register further aligning the mantissas of A and B in accordance with the scale difference and providing the aligned mantissas of A and B; an adder/subtractor of receiving the aligned mantissas of A and B, providing a signed A and B mantissa addition result, and providing a signed A and B mantissa subtraction result; an exponent multiplexer is joined to receive the user supplied opcode, the multiplication preliminary result exponent and the addition/subtraction preliminary result exponent and to provide a result exponent based on the user supplied opcode, said exponent multiplexer providing the multiplication preliminary result exponent as the result exponent if the user supplied opcode selects multiplication, and said exponent multiplexer providing the addition/subtraction preliminary result exponent as the result exponent if the user supplied opcode selects addition or subtraction; an error detector joined to receive the result exponent and to provide an error condition indicator, said error detector providing an error condition indicator if either one or both of the two most significant bits of the result exponent is asserted, and the result exponent being the result exponent when neither of the two most significant bits of the result exponent is asserted; a mantissa multiplexer is joined to receive the user supplied opcode, the signed multiplication result, the signed addition result, and the signed subtraction result and provides the result mantissa based on the user supplied opcode, said mantissa multiplexer providing the signed multiplication result if the user supplied opcode selects multiplication, said mantissa multiplexer providing the signed addition result if the user supplied opcode selects addition, and said mantissa multiplexer providing the signed subtraction result exponent if the user supplied opcode selects subtraction; and wherein the result exponent, result mantissa and the error condition indicator are provided as output.