MANAGING REUSE INFORMATION WITH MULTIPLE TRANSLATION STAGES

摘要

Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. The managing includes: at the second access level, translating from virtual addresses to intermediate physical; at the second access level, determining reuse information for ranges of virtual addresses based on estimated reuse of data stored within a virtual address space; at the first access level, translating from the intermediate physical addresses to physical addresses; at the first access level, determining reuse information for ranges of intermediate physical addresses based on estimated reuse of data stored within an intermediate physical address space; and processing reuse information determined at different access levels to store cache lines in selected portions of a first cache.

主权项

1. A method for managing address translation and caching, the method comprising:
retrieving a first memory page from a storage device in response to a page fault issued after an attempt to retrieve data in the first memory page from a physical address space of a main memory of an external memory system; issuing the attempt to retrieve the data in the first memory page in response to a cache miss issued after an attempt to retrieve the data in the first memory page from a first cache line of a first cache of the external memory system; and managing address translation and caching from a processor that includes (1) at least one memory management unit coupled to the external memory system, and (2) at least one central processing unit configured to run a hypervisor at a first access level and at least one guest operating system at a second access level, the managing including:
at the second access level, translating from virtual addresses in a virtual address space to intermediate physical addresses in an intermediate physical address space;at the second access level, determining reuse information for ranges of virtual addresses in the virtual address space based on estimated reuse of data stored within the virtual address space;at the first access level, translating from the intermediate physical addresses to physical addresses in the physical address space of the main memory;at the first access level, determining reuse information for ranges of intermediate physical addresses in the intermediate physical address space based on estimated reuse of data stored within the intermediate physical address space; andprocessing reuse information determined at different access levels to store cache lines in selected portions of the first cache.