发明名称 |
Reducing input capacitance for high speed integrated circuits |
摘要 |
An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity if formed underneath the pad. Other embodiments are described and claimed.
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申请公布号 |
US2008316662(A1) |
申请公布日期 |
2008.12.25 |
申请号 |
US20070821005 |
申请日期 |
2007.06.21 |
申请人 |
ZENG XIANG YIN;CUI MING DONG;CHRISTENSEN GREGORY V;ABDULLA MOSTAFA NAGUIB;LU DAOQIANG;HE JIANGQI;TANG JIAMIAO |
发明人 |
ZENG XIANG YIN;CUI MING DONG;CHRISTENSEN GREGORY V.;ABDULLA MOSTAFA NAGUIB;LU DAOQIANG;HE JIANGQI;TANG JIAMIAO |
分类号 |
H02H9/00 |
主分类号 |
H02H9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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