Graded well implantation for asymmetric transistors having reduced gate electrode pitches

摘要

In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.

主权项

1. A method, comprising:
forming an implantation mask above a semiconductor region, said implantation mask having a first ion blocking capability above a first transistor internal area of a transistor and having a second ion blocking capability above a second transistor internal area of said transistor, said first and second ion blocking capabilities differing from each other, wherein the first transistor internal area is used for forming a source region and wherein the second transistor internal area is used for forming a drain region; implanting a well dopant species into said first and second transistor internal areas on the basis of said implantation mask; and forming a gate electrode above a channel area of said semiconductor region, said channel area laterally separating said first and second transistor internal areas.