Vertical Thin Film Transistors In Non-Volatile Storage Systems

摘要

Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.

主权项

1. A non-volatile storage system, comprising:
a global bit line; a first vertical thin film transistor (TFT) select device formed over the global bit line, the first vertical TFT select device having a first vertical sidewall and a first gate; a second vertical thin film transistor (TFT) select device formed over the global bit line, the second vertical TFT select device having a second vertical sidewall and a second gate; a dielectric base extending partially between the first vertical sidewall and the second vertical sidewall, the dielectric base having a first notch formed at a first end adjacent to the first vertical sidewall and a second notch formed at a second end adjacent to the second vertical sidewall; and a gate dielectric formed along the first vertical sidewall and separating the first gate from the first vertical sidewall, the gate dielectric formed along the second vertical sidewall and separating the second gate from the second vertical sidewall, the gate dielectric extending vertically in the first notch and the second notch such that the gate dielectric extends below a level of an upper surface of the dielectric base.