Adaptive technique for adjusting signal development across bit lines for read operation robustness in memory circuits

摘要

In one embodiment, a memory array has a pair of bit lines for each column of 1-bit SRAM cells and a word line for each row of cells, where, during a memory read operation, the bit value stored in each cell is detectable by sensing a voltage difference developed between the corresponding bit line pair. A first signal-development circuit is coupled to one bit line to accelerate draining that bit line of charge if a first bit value is stored in the cell, and a second signal-development circuit is coupled to the other bit line to accelerate draining that other bit line of charge if a second, different bit value is stored in the cell. Pulldown devices are provided to ensure that the signal-development circuit operate properly during the pre-charge and voltage difference development phases of the memory read operation, which is now faster due to the signal-development circuits.

主权项

1. An article of manufacture comprising a memory array comprising:
first and second bit lines; at least one cell coupled to the first and second bit lines, wherein a bit value stored in the cell is detectable by sensing a voltage difference developed between the first and second bit lines during a read operation; a first signal-development circuit coupled to the first bit line to accelerate draining the first bit line of charge during the read operation if a first bit value is stored in the cell; and a second signal-development circuit coupled to the second bit line to accelerate draining the second bit line of charge during the read operation if a second bit value, different from the first value, is stored in the cell, wherein each signal-development circuit comprises:a p-type device comprising a gate coupled to the corresponding bit line and a source coupled to a voltage supply; and an n-type device comprising a gate coupled to the drain of the p-type device, a source coupled to a ground, and a drain coupled to the corresponding bit line.