发明名称 Parallel encoding method and system
摘要 A method for parallel multi-dimensional encoding, the method may include receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit; selecting a first set of bits of the first version and a second set of bits of the second version; encoding, in parallel, the first set of bits and the second set of bits; wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result of the encoding of the first set of bits; and wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits.
申请公布号 US9407291(B1) 申请公布日期 2016.08.02
申请号 US201414481681 申请日期 2014.09.09
申请人 AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. 发明人 Weingarten Hanan;Steiner Avi
分类号 H03M13/00;H03M13/27;H03M13/29 主分类号 H03M13/00
代理机构 Reches Patents 代理人 Reches Patents
主权项 1. A method for parallel multi-dimensional encoding, the method comprises: receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit; selecting a first set of bits of the first version and a second set of bits of the second version; encoding, in parallel, the first set of bits and the second set of bits; wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result;wherein the first redundancy result is calculated by applying an encoding process on a first payload that is associated with the first set of bits;wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result; andwherein the second redundancy result is calculated by applying an encoding process on a second payload that is associated with the second set of bits.
地址 Yishun SG