TESTING CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD USING THE SAME

摘要

The present invention enables delay fault detection in a path from a downstream-most combination circuit in a preceding logic circuit to a memory circuit and a path from the memory circuit to a following combination circuit. The present invention provides a testing circuit for detecting a delay fault in a semiconductor integrated circuit including an output control circuit including a plurality of sequential circuits, a combination circuit connected so as to follow the output control circuit and a memory circuit connected so as to follow the combination circuit, and a combination circuit following the memory circuit, wherein the test apparatus inputs a result of predetermined processing of an output of a first sequential circuit from among the plurality of sequential circuits, to the first sequential circuit, stores predetermined data in the memory circuit via the combination circuit according to a result of the predetermined processing at a predetermined alternation of a clock, reads the data from the memory circuit at a next alternation subsequent to the predetermined clock alternating an odd number of times after the predetermined alternation, compares the data and a first state with each other, and performs delay fault detection based on a result of the comparison.

主权项

1. A testing circuit arranged in a semiconductor integrated circuit so as to detect a delay fault in the semiconductor integrated circuit, the semiconductor integrated circuit including a first output control circuit including a plurality of sequential circuits, a first combination circuit connected to follow the first output control circuit and a memory circuit connected to follow the first combination circuit, wherein the testing circuit, under control of a testing apparatus connected to the semiconductor integrated circuit, is configured to:
input a result of predetermined processing being performed on an output of a first sequential circuit leading to an address terminal of the memory circuit via the first combination circuit from among the plurality of sequential circuits, to the first sequential circuit; store predetermined data in the memory circuit via the first combination circuit in accordance with the result of the predetermined processing being performed, at a predetermined alternation timing of a predetermined clock input to the plurality of sequential circuits and the memory circuit; and read the stored data from the memory circuit as a result of delay fault detection in the semiconductor integrated circuit at a next alternation timing subsequent to the predetermined clock alternating an odd number of times after the predetermined alternation timing.