| 摘要 |
PROBLEM TO BE SOLVED: To attain the reduction of a chip size and efficient floor plan correction by making it possible to specify a wiring blank region by the layout design of a semiconductor integrated circuit. SOLUTION: The number of passable wiring per unit region is calculated from wire track information to be extracted from wiring width and wiring interval on the basis of inutted floor plan information and cell arrangement information (2), and the passage route of wiring is estimated from the inputted wiring connection information, and the number of passage wiring per the unit region is calculated (4), and the number of passage wiring per unit region is subtracted from the number of passable wiring per unit region so that the spare number of passable wiring per unit region can be calculated (5), and the information of a wiring blank region to be caused when the spare number of wiring is not 0 can be specified by a display means or the like (6), and floor plan correction such as the reduction of the wiring blank region or the arrangement movement of cells from a wiring congestion region to the wiring blank region is performed (7). COPYRIGHT: (C)2005,JPO&NCIPI
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