Multi-port memory circuits

摘要

A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (SRAM) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit.

主权项

1. A memory circuit, comprising:
a first wordline driver comprising a read wordline driver; a second wordline driver comprising a driver selected from the group consisting of a read wordline driver and a read/write wordline driver; a first bitline and a second bitline; a memory cell coupled to the first and second wordline drivers, and coupled to the first and second bitlines to provide a first voltage on the first bitline complementary to a second voltage of the second bitline; a sense amplifier coupled to the memory cell to amplify low-swing voltages on the first and second bitlines to generate a full-swing logic output; and a latch coupled to the memory cell to latch a full-swing readout on the first bitline to generate a full-swing logic output.